🖥️ Server Hardware Reference Guide

Oracle SPARC servers are enterprise-grade systems built around the SPARC (Scalable Processor ARChitecture) processor family. Unlike x86, SPARC is RISC (Reduced Instruction Set Computing) architecture, designed for extreme reliability, RAS (Reliability, Availability, Serviceability), and mission-critical workloads. All SPARC servers run Oracle Solaris.

CMT was designed to handle thousands of concurrent requests by keeping the CPU pipeline full with many threads, tolerating memory latency by switching threads during cache misses.

T Series Server Models:

• T4-1 / T5-1 / T7-1 / T8-1 — Single socket, 1U/2U rack server. Entry-level CMT.
• T4-2 / T5-2 / T7-2 / T8-2 — Dual socket, 2U rack server. Most common deployment.
• T4-4 / T5-4 / T7-4 — 4-socket server. 512 threads in a T5-4.
• T4-1B / T5-1B / T7-1B — Blade server form factor for Oracle SPARC T4 Blade Server System.
• T5-8 / T7-4 — 8-socket/4-socket max scale CMT configurations.

Software in Silicon — hardware-accelerated capabilities built into the SPARC T7/T8 processor die:

RAS Features (Reliability, Availability, Serviceability):

• Chipkill ECC — corrects multi-bit memory errors. Goes beyond standard single-bit ECC correction.
• Hot-plug DIMMs (M Series) — replace memory modules without downtime.
• CPU/Core retirement — faulty cores are automatically retired and marked offline by the hypervisor. System continues operating.
• Memory mirroring — duplicate all memory writes to a mirror for immediate failover.
• Memory sparing — a DIMM row is held in reserve; activated automatically when a DIMM begins failing.
• Predictive self-healing (ASR) — Automatic System Recovery. Faulty components are detected before failure and automatically taken offline.
• FMA (Fault Management Architecture) — Solaris fault management framework. Every hardware fault generates a structured fault event (UUID) with automated diagnosis and suggested repair action.

The M Series is Oracle's flagship SMP (Symmetric Multiprocessing) server line — designed for absolute maximum reliability for mission-critical workloads like core banking, Oracle databases, and ERP. The M12 supports up to 32 TB of RAM and 384 cores.

M Series RAS features go far beyond T Series — designed for five-nines (99.999%) uptime:

• Dynamic Domains (DR — Dynamic Reconfiguration) — partition the server into independent logical domains, each with its own OS instance. Add or remove CPUs, memory, and I/O from a domain while it is running.
• Dynamic CPU/Memory Addition — hot-add CPU boards and memory boards to a running system. No downtime.
• CPU Locking — lock specific CPU cores to a domain to prevent NUMA migration.
• Mirror Memory Mode — entire memory is mirrored. A single DIMM failure causes zero data loss — the mirror takes over immediately.
• Memory Scrubbing — continuous background ECC scrubbing detects and corrects single-bit errors before they accumulate into multi-bit errors.
• XSCF (eXtended System Control Facility) — M Series management controller (equivalent to ILOM in T Series, but more powerful). Manages hardware partitioning, domains, environmental monitoring.
• Field Replaceable Units (FRUs) — virtually every component is a FRU: CPU boards, memory boards, I/O boards, fans, PSUs, backplanes — all hot-swappable.
• Predictive Failure Analysis (PFA) — monitors component health trends and predicts failures before they occur.

DR is one of the most interview-tested M Series features. It allows zero-downtime hardware changes on a live production system.

The SPARC S7 (introduced 2016) is Oracle's entry/mid-range SPARC server — designed to bring Software in Silicon to a more cost-effective platform.

Key SPARC S7 Features:

• Software in Silicon — full DAX (Data Analytics Accelerator), cryptographic acceleration, Silicon Secured Memory (SSM), and Query Acceleration from T7/M7 generation, available at entry-level price.
• In-Memory Security — Silicon Secured Memory (SSM) detects buffer overflows, heap sprays, and use-after-free attacks in hardware. Enabled with a single kernel parameter change.
• Oracle Solaris Zones — S7 is well-suited for zone-dense deployments due to its thread count. A 2-socket S7-2 with 128 threads can run 20-40 OS zones efficiently.
• Oracle VM for SPARC (LDoms) — S7 supports LDoms for hardware virtualisation. Create guest domains for OS isolation.
• PCIe 3.0 — high-bandwidth I/O for SAN connectivity, 10/25/40 GbE networking.

SSM is one of the most distinctive SPARC S7/T7/T8/M7/M8 features. It uses hardware memory tagging to detect memory corruption attacks in the processor itself, before software-level security can even respond.

The V Series covers Oracle's engineered virtualisation and hybrid platforms that combine SPARC hardware with Oracle software stack integration.

Oracle VM Server for SPARC (LDoms) — Architecture:

• Control Domain — the primary domain that hosts the LDom Manager software. Manages all other domains. Always domain 0.
• Service Domain — provides virtual I/O services (virtual disk, virtual network) to guest domains. Often combined with the control domain.
• I/O Domain — a domain that has direct (PCIe passthrough) access to a physical I/O device. Can share that device as a virtual device to other domains.
• Guest Domain — a virtual machine. Consumes virtual CPUs (vCPUs), virtual memory, and virtual I/O. Can run a full independent Solaris instance.
• vCPU allocation — LDom vCPUs are allocated as SPARC hardware thread strands. A T8-1 (256 threads) can run 8 guest domains × 32 vCPUs each.

All modern multi-socket SPARC servers are NUMA (Non-Uniform Memory Access). Understanding NUMA topology is critical for performance tuning.

• NUMA node — each socket (processor) has its own local memory bank. Memory attached to Socket 0 is "local" to Socket 0 and "remote" to Socket 1.
• NUMA latency — local memory access: ~50ns. Remote memory access: 100-200ns. Binding Oracle DB processes to local NUMA nodes reduces latency significantly.
• On-chip interconnect — SPARC T7/T8 uses on-chip coherent interconnect to link sockets. No separate northbridge chip as in older x86 designs.
• Coherent Interconnect — cache coherence is maintained across all sockets by the hardware. All sockets see a single unified memory address space.

FMA is Solaris's automated hardware and software fault management framework. It is one of the most L3-tested SPARC topics because it integrates hardware and software fault diagnosis.

• DE (Diagnosis Engine) — analyses fault telemetry and produces a structured fault event with UUID, diagnosis, and suggested repair actions.
• FRU (Field Replaceable Unit) — the specific hardware component implicated in a fault. FMA identifies the exact FRU to replace.
• FMRI — Fault Management Resource Identifier — uniquely identifies a resource (service, device, or hardware component) in FMA.
• Suspect list — FMA provides a ranked list of components that may have caused a fault, with percentage certainty.
• Retire — FMA retires faulty CPU cores, memory pages, or other components to continue system operation while repairs are scheduled.

ZFS on SPARC servers benefits directly from Software in Silicon — compression and deduplication are hardware-accelerated, not software. This makes ZFS practical where it would impose too much CPU overhead on x86.